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Tutorial I


Beyond DFT: The Convergence of DFM, Variability, Yield, Test, Diagnosis and Reliability


Dr. Srikanth Venkataraman
Principal Engineer at Intel Corporation


Dr. Robert C. Aitken
IEEE Fellow, ARM Inc

The tutorial goal is to show how design for yield (DFY) and design for manufacturability (DFM) are tightly coupled into what we conventionally think of as test. As process geometries shrink, the line between defects and process variation blurs to the point where it is essentially non-existent. As feature sizes reduced, systematic mechanism-limited yield loss began to appear as a substantial component in yield loss due to the interaction between design and manufacturing. The basics of yield and what fabs do to improve defectivity and manage yield are described. DFM techniques to analyze the design content, flag areas of design that could limit yield, and make changes to improve yield are discussed. In DFM/DFY circles, it is common to speak of defect limited yield, but it is less common to think of test-limited yield, yet this concept is common in DFT (e.g. IDDQ testing, delay testing). Test techniques to close the loop by crafting test patterns to expose the defect prone feature and circuit marginality through ATPG, and by analyzing silicon failures through diagnosis to determine the features that are actually causing yield loss and their relative impact are covered. This tutorial will provide background needed for DFT practitioners to understand DFM and DFY, and see how their work relates to it. The ultimate goal is to spur attendees to conducting their own research in the area, and to apply these concepts in their jobs.

http://www.iti.uni-stuttgart.de/tss2013/data/portraits_big/venkatamaran.jpgDr. Srikanth Venkataraman is a Principal Engineer at Intel Corporation in Hillsboro, OR. He is a strategic planner for test and post-silicon solutions, and manages a group responsible for developing CAD tools for diagnosis, debug and test quality applications in the Design and Technology Solutions group. He has successfully developed and deployed several tools in test, debug and diagnosis used all across Intel. His interests include the areas of VLSI Test (product design for testability and test CAD), Fault diagnosis, Design Verification and Debug, DFM, CAD for VLSI, S/W Engineering and Development. He received his Ph.D. in Electrical and Computer Engineering from the University of Illinois at Urbana-Champaign. He has worked at Texas Instruments and ViewLogic Systems (Sunrise Test System). He has over 60 publications, 3 patents issued and 3 patents pending. He received the best paper award at IEEE VLSI Test Symposium 2000, top 10 papers at IEEE International Test Conference 2000 and the best panel at the IEEE VLSI Test Symposium 99. Intel awards include two Intel Achievement Award (2011, 2006), seven Divisional Recognition Awards (2000, 2002, 2004, 2009 and 2010), Technical Recognition Award (2002), Excellence Award (2001), Discover Award (2000), best papers at Intel Design and Test Technology Conference (2002, 2003). He has presented tutorials on diagnosis, DFM, test and debug at the IEEE Design Automation Conference 2006, ISQED 2007, VLSI Test Symposium 2006, 2004 and 2003, IEEE International Test Conference 2011, 2010, 2008, 2006 and 2004, Design Automation and Test in Europe 2004, European Test Symposium 2009 and 2006, VLSI Design Conference 2008 and 2006, and International Symposium on Testing and Failure Analysis 2008, 2007, 2006, 2004 and 2003.

Dr. Robert C. Aitken is an ARM Fellow and heads the Silicon portion of ARM R&D. His areas of responsibility include low power design, library architecture for advanced process nodes, and design for manufacturability. His research interests include design for variability, defect analysis, and fault diagnosis. His group has taped out a number of chips, including 4 at or below the 22nm node. He has published over 70 technical papers, on a wide range of topics. Dr. Aitken joined ARM as part of its acquisition of Artisan Components in 2004. Prior to Artisan, he worked at Agilent and HP. He has given tutorials and short courses on several subjects at conferences and universities worldwide. He holds a Ph.D. degree from McGill University in Canada. Dr. Aitken is a senior member of the IEEE, and serves on a number of conference and workshop committees.


 Tutorial II


Power-Aware Testing in the Era of IoT


Dr. Patrick Girard,
CNRS Research Director in the Microelectronics Department of LIRMM


Prof. Nicola Nicolici
Dept. of Electrical and Computer Engineering, McMaster University


Prof. Xiaoqing Wen
Dept. of Creative informatics, Kyushu Institute of Technology

Managing power consumption of circuits and systems is one of the most important challenges for the semiconductor industry in the era of IoT. Power management techniques are used today to control the power dissipation during functional operation. Since the application of these techniques has profound implications on manufacturing test, power-aware testing has become indispensable for low-power LSIs and IoT devices. This tutorial provides a comprehensive and practical coverage of power-aware testing. Its first part gives the background and discusses power issues during test. The second part provides comprehensive information on structural and algorithmic solutions for alleviating test-power-related problems. The third part outlines low-power design techniques and shows how low-power devices can be tested safely without affecting yield and reliability.

https://www.lirmm.fr/~girard/images/photo2.jpgPatrick Girard received the M.S. degree in electrical engineering and the Ph.D.degree in microelectronics from the University of Montpellier, Montpellier, France, in 1988 and 1992, respectively. He is currently a Research Director with the French National Center for Scientific Research(CNRS), and a Chair with the Microelectronics Department, Laboratoire d’Informatique de Robotique et de Microélectronique de Montpellier,Montpellier. His current research interests include all aspects of digital testing and memory testing, reliability and fault tolerance, and test of 3-D integrated circuits. Dr. Girard holds the Technical Activities Chair of the Test Technology Technical Council (TTTC) of the IEEE Computer Society. He has served as a Vice-Chair of the European TTTC of the IEEE Computer Society, and also on numerous conference committees. He is the founder and Editor-in-Chief of the ASP Journal of Low Power Electronics and an Associate Editor of the IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS and the Journal of Electronic Testing-Theory and Applications (Springer). He is a Golden Core Member of the IEEE Computer Society.

NicolaNicola Nicolici received the Dipl. Ing. degree in Computer Engineering from the “Politehnica” University of Timisoara, Romania, in 1997 and the Ph.D. degree in Electronics and Computer Science from the University of Southampton, U.K., in 2000. His research interests are in the area of computer-aided design and test for integrated circuits and systems. He has authored over 120 papers in this area.

Xiaoqing WenXiaoqing Wen received the B.E. degree from Tsinghua University, China, in 1986, the M.E. degree from Hiroshima University, Japan, in 1990, and the Ph.D. degree from Osaka University, Japan, in 1993. From 1993 to 1997, he was an Assistant Professor at Akita University, Japan. He was a Visiting Researcher at University of Wisconsin, Madison, USA, from Oct. 1995 to Mar. 1996. He joined SynTest Technologies, Inc., USA, in 1998, and served as its Chief Technology Officer until 2003. In 2004, he joined Kyushu Institute of Technology, Japan, where he is currently a Professor and the Chair of the Department of Creative Informatics. He founded Dependable Integrated Systems Research Center in 2015 and served as its Director until 2017. His research interests include VLSI test, diagnosis, and testable design. He co-authored and co-edited two books: VLSI Test Principles and Architectures: Design for Testability (Morgan Kaufmann, 2006) and Power-Aware Testing and Test Strategies for Low Power Devices (Springer, 2009). He holds 43 U.S. Patents and 14 Japan Patents on VLSI testing. He received the 2008 IEICE-ISS Best Paper Award for his pioneering work on Xfilling-based low-capture-power test generation. He is a fellow of the IEEE, a senior member of the IPSJ, and a member of the IEICE. He is serving as associate editors for IEEE Transactions on Computer Aided Design, IEEE Transactions on VLSI, and the Journal of Electronic Testing: Theory and Applications.

Embedded Tutorial I


Machine Learning and Its Applications in Test


Dr. Yu Huang
Mentor, A Siemens Business

In this tutorial, we will start by covering the basics of machine learning. We will proceed to give a brief overview of the new and exciting field of deep learning. We will show how easy it is to try using machine learning and deep learning, thanks to powerful, free libraries. After offering the required background in machine learning, we will review several important papers in the field of DFT, diagnosis, yield learning, and root cause analysis, which use machine learning algorithms for solving various problems. Finally, we will propose future research directions in the area of testing, where we think machine learning (especially deep learning) can make a big impact.

Dr. Yu Huang is a Principal Engineer in the Silicon Test Systems Division of Mentor, A Siemens Business. His research interests include VLSI SoC testing, ATPG, compression and diagnosis. He has a BS in electronic science and an MS in semiconductor devices and technology, both from Nankai University, China; and a PhD in electrical and computer engineering from the University of Iowa. He holds 27 US patents and has 9 more patents pending. He has published more than 100 papers on leading IEEE Journals, conferences and workshops. He is a senior member of the IEEE. He has served as technical program committee member for DAC, ITC, ATS, ETS, ASPDAC, NATW and some other conferences and workshops in the testing area.