Keynotes & Invited Talk   Technical Program>Keynotes & Invited Talk
 

Keynote 1

 

Title:

Security along SoC Design Lifecycle: Current Practices and Challenges Ahead

Presenter:

Prof. Mark M. Tehranipoor
Intel Charles E. Young Preeminence Endowed Chair Professor in Cybersecurity
Florida Institute for Cybersecurity Research, University of Florida

Abstract:
System-on-chip (SoC) security has received significant attention in the past several years due mainly to its prevalence in internet of things (IoT) devices, cyber physical systems, and embedded computing systems. Security of SOCs has become even a greater concern due to the globalized design, fabrication, and assembly processes. The complexity of today’s electronic components and systems supply chain has made SoCs increasingly vulnerable to intentional and unintentional attacks (malicious activities, information leakage, side channel signal leakage, confidentiality attacks and integrity violations). In this talk, we will first analyze these vulnerabilities and threats. We will then present challenges dealing with emerging attacks and threats in SoCs and present potential solutions and set of security rules to addressing them.

Biography:
TehranipoorMark Tehranipoor is currently the Intel Charles E. Young Preeminence Endowed Chair Professor in Cybersecurity at the ECE Department, University of Florida. He is also currently serving as the Associate Chair for Research and Strategic Initiatives at the ECE Department, and as Director for Florida Institute for Cybersecurity Research (FICS). His current research interests include: IoT security, hardware security and trust, supply chain risk management and security, counterfeit electronics detection and prevention and reliable circuit design. Dr. Tehranipoor has published over 400 journal articles and refereed conference papers and has given more than 175 invited talks and keynote addresses since 2006. He is a recipient of 13 best paper awards and nominations, as well as the 2008 IEEE Computer Society (CS) Meritorious Service Award, the 2012 IEEE CS Outstanding Contribution, the 2009 NSF CAREER Award, and the 2014 MURI award.
He serves on the program committee of more than a dozen leading conferences and workshops. He served as Program and General Chairs of several leading conferences and workshops. He co-founded a new symposium called IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) and served as HOST-2008 and HOST-2009 General Chair (http://www.hostsymposium.org/). He is currently serving as HOST’s Chair of Steering Committee. He is also the co-founder of Trust-Hub (www.trust-hub.org) and Asian HOST (http://asianhost.org/2017/). He serves as co-EIC for newly established Journal on Hardware and Systems Security (HaSS). He also served as an Associate EIC for IEEE Design & Test, an IEEE Distinguished Speaker, and an ACM Distinguished Speaker from 2010 to 2014. He is currently serving as an Associate Editor for JETTA, JOLPE, Transactions on VLSI (TVLSI), and Transactions on Design Automation for Electronic Systems (TODAES). Dr. Tehranipoor is a Fellow of IEEE, a Golden Core Member of the IEEE, and Member of ACM and ACM SIGDA. He is currently serving as IEEE Ambassador on Cybersecurity.


                Keynote 2

 

Title:

Robustness Challenges in the Internet of Things

Presenter:

Dr. Yervant Zorian
Synopsys Fellow & Chief Architect

Abstract:
The Internet of Things (IoT) is an extremely fragmented market and can be defined as anything from sensors to small servers. It is estimated that over 30 billion IoT devices will ship by 2020. The ability to sense countless amounts of information that communicates to the cloud is driving innovation into IoT applications, such as in wearable devices (for health, fitness or infotainment applications) and in machine-to-machine applications (in smart appliances, smart cities or commerce).  It has become crucial for today’s IoT chips to use a range of new solutions during the design stage to ensure the robustness of manufacturing test, field reliability and security. DFT designers need to use new test and reliability solutions to enable power reductions during test, concurrent test, isolated debug and diagnosis, pattern porting, calibration, and uniform access. Moreover, the per unit IoT price remains a key factor in high volume production. Thus, minimizing the test cost while meeting the above technical issues is one of the major challenges of the IoT industry. This keynote, besides discussing the key trends and challenges of IoT, will cover solutions to handle the wide range of potential robustness challenges during all periods of the IoT lifecycle from design, post silicon bring-up, volume production, to in-system operation.

Biography:
Dr. Yervant Zorian is a Chief Architect and Fellow at Synopsys, as well as President of Synopsys Armenia. Formerly, he was Vice President and Chief Scientist of Virage Logic, Chief Technologist at LogicVision, and a Distinguished Member of Technical Staff AT&T Bell Laboratories. He is currently the President of IEEE Test Technology Technical Council (TTTC), the founder and chair of the IEEE 1500 Standardization Working Group, the Editor-in-Chief Emeritus of the IEEE Design and Test of Computers and an Adjunct Professor at University of British Columbia. He served on the Board of Governors of Computer Society and CEDA, was the Vice President of IEEE Computer Society, and the General Chair of the 50th Design Automation Conference (DAC).
A Fellow of the IEEE since 1999, Dr. Zorian was the 2005 recipient of the prestigious Industrial Pioneer Award for his contribution to BIST, and the 2006 recipient of the IEEE Hans Karlsson Award for diplomacy. He received the IEEE Distinguished Services Award for leading the TTTC, the IEEE Meritorious Award for outstanding contributions to EDA, and in 2014, the Republic of Armenia's National Medal of Science.


Keynote 3

 

Title:

What Else Is Needed for Telecom Product Reliability beyond Manufacturing Test?

Presenter:

Dr. Xinli Gu
Senior Director with Huawei Technologies, USA

Abstract:
From electronic product quality standpoint, manufacturing tests can efficiently eliminate defected products caused by manufacturing. However, this is only one of the steps to guarantee product reliability. In telecom industry, product reliability is really an end-to-end engineering process. It involves design correctness, design for reliability and tolerance, operation monitoring, self-correction and recovery, etc. beyond manufacturing test. This presentation covers a typical telecom industry practice for product reliability. Some of the techniques, tools, processes and flows will be discussed.

Biography:
Xinli GuDr. Xinli Gu is a Senior Director with Huawei Technologies, USA since 2011, leading design solution and driving corporate process for product quality and reliability. Before joining Huawei, he was a director with Cisco Systems, Inc. for 12 years, responsible for corporate level product quality, Time-to-Market, manufacturing test and diagnosis, and product yield improvement. Xinli also worked for Synopsys in California and Ericsson in Sweden. He received a BSc in Computer Science from Shanghai Jiao Tong University, and MSc/PhD in Computer Science and Information from Linkoping University, Sweden. He is an active IEEE member and leads system/ASIC DFT/test/reliability areas.