Symposium overview

 

The Asian Test Symposium (ATS) provides an open forum for researchers and industrial practitioners from all countries of the world to exchange innovative ideas on system, board, and device testing with design, manufacturing and field consideration in mind.
Symposium: October 15~18, 2018
Submission deadline:May 20, 2018
Notification of acceptance: June 30, 2018
Camera ready due: July 20, 2018
Below is a link to access the Author Submission Site:
https://ieeecps.org
Camera ready due: July 20, 2018
The site is provided to help you in the preparation and submission of your final paper as it will be published in the proceedings.

Original papers on, but not limited to, the following areas are invited.

  • Analog/Mixed-Signal Test
  • Automatic Test Generation
  • Board Test and Diagnosis
  • Boundary Scan Test
  • Built-In Self-Test (BIST)
  • Defect-Based Test
  • Delay and Performance Test
  • Dependability and Functional Safety
  • Design for Test (DFT)
  • Diagnosis and Silicon Debug
  • Economic of Test
  • Failure Analysis
  • Fault Modeling and Simulation
  • Fault Tolerance
  • GPU Test
  • High-Speed I/O Test
  • Low-Power IC Test
  • Memory Test and Repair
  • MEMS Test
  • Multi-/Many-core Processor Test
  • Nanotechnology Test
  • On-line Test
  • Power/Thermal/Reliability Issues in Test
  • Reconfigurable System Test
  • Reliability
  • RF Test
  • Hardware-oriented Security and Trust
  • Self-Repair
  • Sensor Test
  • SiP, Stacked, 3D IC Test
  • SoC Test
  • Standards in Test
  • Statistical Learning in Test
  • Test Compression
  • Test Quality
  • Test Synthesis
  • Validation and Verification
  • Yield Analysis and Enhancement

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